Interrupts & RTI
Intro to Interrupts Document Summary
Interrupt Vector Table: The MC9S12XDP512 uses an interrupt vector table to store the addresses of interrupt service routines (ISRs). Each interrupt source has a specific vector address in this table. Interrupt Priority: Interrupts are prioritized based on their vector number. Lower vector numbers have higher priority, meaning they are serviced before higher-numbered vectors.
Global Interrupt Masking: The microcontroller can globally enable or disable interrupts using the EnableInterrupts and DisableInterrupts macros. This is managed by setting or clearing the I bit in the Condition Code Register (CCR).
Non-Maskable Interrupts: Certain critical interrupts, known as non-maskable interrupts, cannot be disabled and must always be serviced. Local Interrupt Masking: Individual interrupts can be enabled or disabled by setting or clearing specific bits in their corresponding control registers. For example, enabling the interrupt for PIT1 involves setting BIT1 in the relevant register.
Interrupt Handling Process: When an interrupt occurs, the MCU saves the current program counter (PC) and status registers, executes the ISR, and then restores the saved PC and status registers to resume normal program execution.